Yes, it's a fact that I love exploring the upper echelon of high-end audio gear, but that doesn't preclude my fascination and enthusiasm for high-end audio products that are more affordable and at the reach of many more audiophiles and music lovers.
It's a far more difficult task to achieve something at a more affordable level than it is with a product where the cost of production and the materials used are not relevant factors.
Mono and Stereo now have over 800,000 readers from all over the world, including many readers who keep asking me to discover more products with down-to-earth pricing.
Mono and Stereo operate almost around the clock, and I can only write a certain number of reviews per year, as there is a lot of work behind the full operation.
What you won't see at M & S are negativity and bad reviews. If a product doesn't work as advertised or doesn't perform at the level needed, we simply don't review it. Long-time M & S readers have figured this out already, but perhaps for the new readers and followers, it is worth putting it out there.
While many upscale high-end audio manufacturers stagnate and rest on their laurels, a lot of smaller, new brands are trying to push the boundaries of digital by other means.
As you'll read in the following chapter, HIBIKI SD DAC is one of such and comes with a far more intriguing and complex story as well as sonic liquidity than is usually the case.
THE STORY OF SOSOLAR AND HIBIKI
SOSOLAR (SOSO), who used to work at ARM, had difficulty finding a DAC with suitable sound and satisfactory price while studying in the UK, so he came up with the idea of building one himself.
There is already a wide range of DACs available, using either discrete technology or integrated chip. SOSO himself is a very cautious person and didn't want to pick up the integrated chip that comes with any kind of bugs, let alone the so-called hidden menu of the integrated chip, such as the configuration of additional registers, causing a mode of operation that is not in the specification.
In addition, SOSO is also not favoring integrated chips in the operation mode of the opaque part, as some chips before modulation, often do SRC operation. Not always is known what is done inside, such as the algorithm used, operating frequency, efficiency, configurable degree, etc., and SOSO tends not to trust such devices without transparent information.
While integrated chips evolve and implement innovative approaches, SOSO, preferred to not follow the trend of constant changes, and do rather something meaningful at the base level and then use that architecture for a long time.
For this reason, HIBIKI SDS DAC adopts a discrete design. Once the decoding architecture is fixed, only the algorithm and the tuning layer need to be adjusted in the future. This proprietary design also bypasses the bottleneck problems of acquiring the needed part that most manufacturers have faced in recent years.
Once the general direction was established, the next challenge was to select a specific decoding architecture. SOSO examined the major architectures on the market, such as the hardware architectures of String-Dac and R2R, and the algorithm architectures of PCM and SDM.
In 2015, SOSO set the technology roadmap. First, start with R2R with low algorithm requirements but high hardware requirements, and then develop string DAC with high algorithm requirements but low hardware requirements.
R2R has very high requirements for algorithms. Fortunately, SOSO has a background in algorithms itself and is very familiar with SRC algorithms.
And with this design, low-pass filters are needed. Usually, low-pass filters can be classified into several common characteristics according to the Q value, such as Chebyshev, Bessel, Butterworth, and so on. The sound of each filter characteristic is also very different. For example, the sound of Chebyshev is more aggressive and rich in overtones, Bessel is more rational, and Butterworth is more torpid. SOSO used the Bezier characteristic curve when designing BDS because he believes that the Bezier waveform is closer to the ideal and that our ear can also confirm this view.
R2R alone was not nearly enough to achieve the goal of SOSO. The other crucial area to overcome was the clock. It is generally assumed that the clock is not sensitive to R2R. The context of this sentence is that R2R is not sensitive to the clock compared to the SDM architecture.
Nevertheless, basically, all DACs are very sensitive to the clock, but the frequency of R2R is low, and the clock is often easier to implement properly, but the frequency of SDM is very high, which puts high demands on the power supply, wiring, and performance of the clock.
There are several hardware implementations of the audio clock source, synchronous clock source, and asynchronous clock source. At present, asynchronous clock sources are widely adopted. The advantage is that they are very convenient to use. To simplify, one just needs to witch the corresponding crystal oscillator according to the frequency. Besides, it is very convenient to buy high precision and low noise oscillators in the market, and the reasonable well sound is relatively simple to achieve, so many manufacturers like to use them.
But on the other hand, once an asynchronous clock source like an oscillator is set, the system loses its scalability.
Compared to the convenience of using asynchronous clocks, SOSO was more concerned about scalability because he believes that there will be better products no matter how low noise or good the oscillators are. At this point, the asynchronous clock system is very closed in terms of architecture.
SOSO has decided to synchronize clocks.
There are many problems with synchronous clock sources that need to be solved: Phase-locked loop, power supply, crystal oscillator.
Phase-locked-loop circuits can rely on integrated chips, but SOSO doesn't trust them either. For one thing, the performance is not good enough, and for another, the chip may fail in due course.
Consequently, SOSO began to develop phase-locked loop technology from scratch in 2017. The essence of the phase-locked loop is to calibrate the feedback source by generating an error voltage through a suitable reference source and the time base error of the feedback source. There can be many sources of noise and error in this process. First, the frequency divider will have a phase error, which manifests itself here mainly as phase noise degradation of the intermediate frequency.
Once all the software, hardware, and layout were determined, the focus was turned back to the main principle of HIBIKI SDS DAC, the sound.
Although SOSO comes from an engineering background, he is not averse to the process of "tuning". He has always believed that so-called tuning is an understanding of sound. A higher, necessary task.
Example. Theoretically, we can't change the frequency of the violin directly, but we can adjust the harmonic frequency of the violin to a distribution that better expresses the tone of the violin.
We can't change the frequency of the piano either, but we can slow down the speed of the piano a little to soften the intense piano sound.
This of course requires some understanding of the timbre of musical instruments and music. To achieve the ideal timbre and music, SOSO has not only adjusted the circuit architecture itself but also focused on the composition of the parts.
SOSO discovered that by introducing a small phase delay in different frequency bands, a highly interesting auditory sense was sparked. Although the use of phase does not affect indicators such as distortion (THD), it does bring some change to the sound.
Furthermore. Bandwidth is a very interesting technical attribute. It is generally assumed that the device only needs to be configured to 1/2 bandwidth to achieve the quality needed, but in reality, this is not always the case. Higher bandwidth can bring a finer, denser sound quality, but at the same time, it can make the music sound dry. Conversely, lower bandwidth can bring a more pleasing weight to the music, but reduce the density of high and low-frequency information.
The more research SOSO did, the more he discovered that the core conservation or design problem of his system was not limited to the circuit itself, but also the oscillator. The oscillator used in the phase-locked loop is a special called voltage-controlled oscillator.
The voltage-controlled oscillator usually has several characteristics, the range of the control voltage and the phase noise. Generally, the control voltage range is inversely proportional to the phase noise. The narrower the control range, the better the phase noise.
The story goes on, but since I don't want the review to be solely based only on this part, I'll stop here. I'm sure you got a pretty good idea of the effort that went into the HIBIKI.
HIGHLIGHTS
Here are some highlights of the HIBIKI SDS, String Decoding System Fully Discrete DAC:
Digital Signal Conditioner Ground Isolation
- Ultra-Low Phase Noise Re-Trigger
- Robust Signal Conditioning
Ultra-low phase noise re-clocking
- Wide Band Inductor -based LCVCO
- Narrow Band Crystal VCXO DSD
- PCM specified FIFO databank re-trigger
Digital filter
- No pre- or post-ringing
Delta-Sigma Modulator
- All up to SDM1024, 5bits
PCM/DSD signal conditioning
- String decoding network 36 code programmable decoding array
- Phase and offset alignment
Discrete Class-A output stage with non-negative feedback
- Discrete Class AB, No-negative Feedback
PCM /DSD DIGITAL SIGNAL PROCESSING
PCM is upscaled to a 1024x rate, as is DSD. In general, DSD cannot be processed, but HIBIKI SDS DAC has reverse-analyzed the principle of DSD and specifically developed a modulator structure that allows DSD to be directly modulated 1024 times as input.
When the DSD128 information stream comes from HDMI or USB, SDS can be directly modulated from DSD128 to DSD1024 times without going through the PCM jump process at all, and there is no information loss in this process.
SDM1024, 5BITS
At the heart of DA, the HIBIKI SDS DAC uses a high-order sigma-delta modulator. Both PCM and DSD are modulated directly to a 5-bit 1024x rate. Generally, modulation of 1 bit is DSD, but five bits is inherently more than 1 bit of information, 2 to the power of 5, which is 32 times, and the signal-to-noise ratio is also 30db.
Generally, the internal modulation frequency of the DA chip is 256 times, which can quantify the noise to 50k, but the SDS modulation frequency is 1024 times, which can push the quantization noise to 100k, the high-frequency information abounds and the details are richer.
DIGITAL SIGNAL CONDITIONER
Ground Isolation
All input devices of SDS /BDS are equipped with a ground isolation circuit, which can completely isolate the interference of the front ground wire to the machine.
Ultra-Low Phase Noise Re-Trigger
A great deal of effort and expertise has gone into avoiding and eliminating the source of additive phase noise from the signal transmission. A special circuit that can reduce the additive phase noise has been designed and implemented.
Robust signal conditioning
SDS/ BDS is quite tolerant of digital input signal requirements, from 100mV to 5V, a sinusoidal square wave can be seamlessly adopted.
ULTRA LOW NOISE REGULATED POWER SUPPLY
A special power architecture is adopted to achieve full frequency power noise of - 150db, which highlights more details
OPERATIONAL
SDS
SDS stands for a String Decoding System. Since the decoding structure of SDS is a multi-bit resistor string, it is called a string. SDS has an upscaling function, 5bit SDM 1024. No matter what sound source, you can upscale with just one click. Currently, 5bit SDM 1024 seems to be a novelty on the market.
SDS UPSAMPLING
When the PLL button is pressed, upsampling takes place. When the PLL key is not pressed, no oversampling is in use
HIBIKI SDS DAC supports both WCK and MCK clock signals and also supports dual clock inputs.
THE MUSIC
CONCLUSION
Matej Isak
PRICE
- $3,700.00
TECHNICAL SPECIFICATIONS
